AMD Claims Rack-Scale CPU Advantage As Agentic AI Reshapes Data Centre Infrastructure

The rise of agentic AI is forcing a rethink of data centre architecture, and AMD argues its EPYC processor line is positioned to benefit from the shift.

As enterprises move from experimental AI chatbots to production-grade agentic systems – where autonomous software agents perform multi-step tasks across applications and databases – the computational demands on CPUs, not just GPUs, are increasing.

AMD has published performance projections that it claims demonstrate rack-level throughput advantages for its EPYC processors over competing silicon from Nvidia and Intel, under a standardised 100 kW power constraint.

The CPU Question Behind Agentic AI

The narrative around AI infrastructure has been dominated by GPUs. But production agentic systems are not solely about model inference. Every agent depends on orchestration logic, transactional databases, web and API endpoints, key-value stores, in-memory caches and middleware that coordinate work, hold state and broker requests across the system.

These services are overwhelmingly CPU-bound, and they scale with the number of concurrent agents rather than the size of any single model.

AMD’s argument is that the processor platform hosting these services becomes a primary factor in determining how many agents an enterprise can run and at what cost. It is at this layer, the company contends, where general-purpose CPU capacity sets the ceiling – not accelerator peak performance.

The company points to a changing CPU-to-GPU ratio in data centre deployments. Where GPU-centric AI designs have typically used ratios of 1:4 or 1:8 in favour of GPUs, agentic workloads are pushing that ratio to 1:1 or higher in favour of CPUs, according to AMD.

Rack-Level Performance, Not Component Benchmarks

Central to AMD’s argument is that component-level benchmarks describe a chip but do not describe what a customer can deploy. Data centres are provisioned in racks, and racks are bounded by a fixed power and thermal budget, finite floor space, software compatibility requirements and operational readiness.

The question that determines real capacity, AMD argues, is not how fast a single socket performs but how much useful work fits inside a 100 kW rack.

All configurations in AMD’s analysis are normalised to a modelled 100 kW rack built on dual-socket (2P) platforms, comparing deployable service capacity rather than isolated peak processor behaviour.

AMD’s Projected Numbers

AMD’s modelling covers six workloads: general-purpose computing (SPECrate 2017 Integer Rate), server-side Java (a SPECjbb2015-derived workload), web serving (NGINX with WRK), key-value store (Redis), in-memory caching (Memcached with memtier_benchmark) and relational databases (TPROC-C, a TPC-C-derived OLTP proxy on MySQL).

Across these workloads, AMD claims its EPYC 9965 “Turin” processor (192 cores) delivers a 2.37x normalised geometric mean advantage over the Nvidia Vera baseline (88 cores), with Intel’s Xeon 6980P “Granite Rapids-AP” (128 cores) achieving 1.46x over Nvidia Vera.

AMD projects that its next-generation EPYC “Venice” processor (256 cores) will extend the advantage to 3.30x over Nvidia Vera.

The per-workload breakdown, normalised to Nvidia Vera at 1.0, is as follows:

For SPECrate 2017 Integer Rate, AMD EPYC 9965 scored 1.60 and Venice is estimated at 2.40, while Intel Xeon 6980P came in at 1.47. In server-side Java, the figures were 2.93 for AMD EPYC 9965, 3.76 for Venice and 2.34 for Intel. Web serving returned 2.37 for EPYC 9965, 3.30 for Venice and 1.18 for Intel. Key-value store performance was 2.23 for EPYC 9965, 3.10 for Venice and 1.31 for Intel. In-memory caching produced scores of 2.49 for EPYC 9965, 3.47 for Venice and 0.93 for Intel. Relational database testing showed 2.91 for EPYC 9965, 4.05 for Venice and 1.99 for Intel.

How The Estimates Were Derived

AMD’s methodology document provides detail on how the projections were calculated, and it reveals several layers of estimation that should be considered when interpreting the results.

For Nvidia Vera, no direct benchmark data was used. Instead, AMD derived Vera’s performance by scaling above Nvidia Grace Superchip platform results by applying a 1.63x factor. That factor is based on the overall geometric mean of select test results from a Phoronix review published in May 2026.

AMD and Intel figures for the EPYC 9965 and Xeon 6980P are based on published AMD testing and third-party results from prior comparisons against the Nvidia Grace Superchip.

For AMD EPYC Venice, single-node performance is estimated at roughly 1.7x that of the EPYC 9965, based on SPECrate 2017 Integer Rate projections and internal testing.

Rack-level performance is then derived by multiplying estimated node count per rack (within the 100 kW constraint) by single-node performance. System power estimates are based on processor TDPs and component estimates.

The methodology document notes that these performance derivations “are not directly comparable but suggest similar generational gains, subject to workload characteristics.”

Rack Density Comparisons

AMD also draws attention to core density per rack as a proxy for deployable compute capacity.

Under AMD’s modelling, an EPYC Turin deployment in a liquid-cooled rack supports more than 27,000 CPU cores per rack. The company projects EPYC Venice will scale beyond 36,000 cores in the same rack class. By comparison, Nvidia Vera in a dual-socket configuration delivers 22,500 cores per rack.

AMD is quick to note that these deployments run on standard liquid-cooled data centre equipment within the x86 software ecosystem, requiring no new rack architecture. The company frames this as preserving software continuity and reducing migration friction for enterprises.

Per-Core Performance Claims

Beyond rack-level throughput, AMD also makes claims about per-core performance.

The company estimates that the EPYC Venice 64-core CPU will deliver a 27 per cent performance-per-core advantage compared to the Nvidia Vera 88-core processor, measured using SPECrate 2017 Integer Rate on dual-socket platforms.

Even at a higher core count, the 96-core Venice variant is projected to deliver 11 per cent higher performance-per-core than Vera’s 88-core processor.

Caveats To Consider

AMD’s analysis, while detailed in its methodology, contains several layers of estimation that warrant scrutiny.

The Nvidia Vera baseline is not based on direct benchmarking of the Vera processor itself. It is derived from Nvidia Grace results scaled by a factor drawn from a third-party review. This means the entire comparison framework rests on an estimated baseline.

The Venice projections are similarly forward-looking, based on internal testing and modelled scaling rather than production hardware benchmarks.

The methodology document acknowledges these limitations, stating the results “are intended to provide directional comparison rather than direct measured rack benchmarks.”

The workload suite also does not model full end-to-end agent pipelines. It isolates the infrastructure layers those pipelines depend on, which means real-world performance in a production agentic environment could vary depending on workload mix and system configuration.

What It Means For Data Centre Planning

Regardless of the precise numbers, AMD’s broader point about the changing shape of AI infrastructure resonates with industry trends. As agentic AI moves from proof-of-concept to production, the supporting CPU infrastructure – databases, caches, orchestration services, web front ends and API endpoints – must scale alongside GPU-accelerated inference.

For enterprises evaluating their next round of data centre investments, the question is shifting from raw GPU throughput alone to how efficiently CPU and GPU resources can be balanced within fixed power and space constraints.

AMD’s pitch is that its current-generation EPYC processors can address this need on shipping platforms and within the existing x86 software ecosystem, while competitors are still positioning future architectures. Whether the projected advantages hold up under independent, production-scale testing remains to be seen.

Last Updated on June 26, 2026 by Nick Ross